Enum Interrupt
#[repr(u16)]pub enum Interrupt {
Show 77 variants
WIFI_MAC = 0,
WIFI_MAC_NMI = 1,
WIFI_PWR = 2,
WIFI_BB = 3,
BT_MAC = 4,
BT_BB = 5,
BT_BB_NMI = 6,
LP_TIMER = 7,
COEX = 8,
BLE_TIMER = 9,
BLE_SEC = 10,
I2C_MASTER = 11,
ZB_MAC = 12,
PMU = 13,
EFUSE = 14,
LP_RTC_TIMER = 15,
LP_UART = 16,
LP_I2C = 17,
LP_WDT = 18,
LP_PERI_TIMEOUT = 19,
LP_APM_M0 = 20,
LP_APM_M1 = 21,
FROM_CPU_INTR0 = 22,
FROM_CPU_INTR1 = 23,
FROM_CPU_INTR2 = 24,
FROM_CPU_INTR3 = 25,
ASSIST_DEBUG = 26,
TRACE = 27,
CACHE = 28,
CPU_PERI_TIMEOUT = 29,
GPIO = 30,
GPIO_NMI = 31,
PAU = 32,
HP_PERI_TIMEOUT = 33,
MODEM_PERI_TIMEOUT = 34,
HP_APM_M0 = 35,
HP_APM_M1 = 36,
HP_APM_M2 = 37,
HP_APM_M3 = 38,
LP_APM0 = 39,
MSPI = 40,
I2S0 = 41,
UHCI0 = 42,
UART0 = 43,
UART1 = 44,
LEDC = 45,
TWAI0 = 46,
TWAI1 = 47,
USB_DEVICE = 48,
RMT = 49,
I2C_EXT0 = 50,
TG0_T0_LEVEL = 51,
TG0_T1_LEVEL = 52,
TG0_WDT_LEVEL = 53,
TG1_T0_LEVEL = 54,
TG1_T1_LEVEL = 55,
TG1_WDT_LEVEL = 56,
SYSTIMER_TARGET0 = 57,
SYSTIMER_TARGET1 = 58,
SYSTIMER_TARGET2 = 59,
APB_SARADC = 60,
MCPWM0 = 61,
PCNT = 62,
PARL_IO = 63,
SLC0 = 64,
SLC1 = 65,
DMA_IN_CH0 = 66,
DMA_IN_CH1 = 67,
DMA_IN_CH2 = 68,
DMA_OUT_CH0 = 69,
DMA_OUT_CH1 = 70,
DMA_OUT_CH2 = 71,
SPI2 = 72,
AES = 73,
SHA = 74,
RSA = 75,
ECC = 76,
}
Expand description
Enumeration of all the interrupts.
Variants§
WIFI_MAC = 0
0 - WIFI_MAC
WIFI_MAC_NMI = 1
1 - WIFI_MAC_NMI
WIFI_PWR = 2
2 - WIFI_PWR
WIFI_BB = 3
3 - WIFI_BB
BT_MAC = 4
4 - BT_MAC
BT_BB = 5
5 - BT_BB
BT_BB_NMI = 6
6 - BT_BB_NMI
LP_TIMER = 7
7 - LP_TIMER
COEX = 8
8 - COEX
BLE_TIMER = 9
9 - BLE_TIMER
BLE_SEC = 10
10 - BLE_SEC
I2C_MASTER = 11
11 - I2C_MASTER
ZB_MAC = 12
12 - ZB_MAC
PMU = 13
13 - PMU
EFUSE = 14
14 - EFUSE
LP_RTC_TIMER = 15
15 - LP_RTC_TIMER
LP_UART = 16
16 - LP_UART
LP_I2C = 17
17 - LP_I2C
LP_WDT = 18
18 - LP_WDT
LP_PERI_TIMEOUT = 19
19 - LP_PERI_TIMEOUT
LP_APM_M0 = 20
20 - LP_APM_M0
LP_APM_M1 = 21
21 - LP_APM_M1
FROM_CPU_INTR0 = 22
22 - FROM_CPU_INTR0
FROM_CPU_INTR1 = 23
23 - FROM_CPU_INTR1
FROM_CPU_INTR2 = 24
24 - FROM_CPU_INTR2
FROM_CPU_INTR3 = 25
25 - FROM_CPU_INTR3
ASSIST_DEBUG = 26
26 - ASSIST_DEBUG
TRACE = 27
27 - TRACE
CACHE = 28
28 - CACHE
CPU_PERI_TIMEOUT = 29
29 - CPU_PERI_TIMEOUT
GPIO = 30
30 - GPIO
GPIO_NMI = 31
31 - GPIO_NMI
PAU = 32
32 - PAU
HP_PERI_TIMEOUT = 33
33 - HP_PERI_TIMEOUT
MODEM_PERI_TIMEOUT = 34
34 - MODEM_PERI_TIMEOUT
HP_APM_M0 = 35
35 - HP_APM_M0
HP_APM_M1 = 36
36 - HP_APM_M1
HP_APM_M2 = 37
37 - HP_APM_M2
HP_APM_M3 = 38
38 - HP_APM_M3
LP_APM0 = 39
39 - LP_APM0
MSPI = 40
40 - MSPI
I2S0 = 41
41 - I2S0
UHCI0 = 42
42 - UHCI0
UART0 = 43
43 - UART0
UART1 = 44
44 - UART1
LEDC = 45
45 - LEDC
TWAI0 = 46
46 - TWAI0
TWAI1 = 47
47 - TWAI1
USB_DEVICE = 48
48 - USB_DEVICE
RMT = 49
49 - RMT
I2C_EXT0 = 50
50 - I2C_EXT0
TG0_T0_LEVEL = 51
51 - TG0_T0_LEVEL
TG0_T1_LEVEL = 52
52 - TG0_T1_LEVEL
TG0_WDT_LEVEL = 53
53 - TG0_WDT_LEVEL
TG1_T0_LEVEL = 54
54 - TG1_T0_LEVEL
TG1_T1_LEVEL = 55
55 - TG1_T1_LEVEL
TG1_WDT_LEVEL = 56
56 - TG1_WDT_LEVEL
SYSTIMER_TARGET0 = 57
57 - SYSTIMER_TARGET0
SYSTIMER_TARGET1 = 58
58 - SYSTIMER_TARGET1
SYSTIMER_TARGET2 = 59
59 - SYSTIMER_TARGET2
APB_SARADC = 60
60 - APB_SARADC
MCPWM0 = 61
61 - MCPWM0
PCNT = 62
62 - PCNT
PARL_IO = 63
63 - PARL_IO
SLC0 = 64
64 - SLC0
SLC1 = 65
65 - SLC1
DMA_IN_CH0 = 66
66 - DMA_IN_CH0
DMA_IN_CH1 = 67
67 - DMA_IN_CH1
DMA_IN_CH2 = 68
68 - DMA_IN_CH2
DMA_OUT_CH0 = 69
69 - DMA_OUT_CH0
DMA_OUT_CH1 = 70
70 - DMA_OUT_CH1
DMA_OUT_CH2 = 71
71 - DMA_OUT_CH2
SPI2 = 72
72 - SPI2
AES = 73
73 - AES
SHA = 74
74 - SHA
RSA = 75
75 - RSA
ECC = 76
76 - ECC